Performance and reliability of processors are important factors in designing computer systems. Because processors are continually becoming more complex, they require more testing and debugging to ensure reliable performance. A program typically undergoes a debugging process to find and correct “bugs” in the operation of the program. As an example, to debug a processor, the processor is placed in a debug or test mode to prevent the processor's execution unit(s) from prefetching and decoding instructions. In this manner, when the processor is in the debug mode, external circuitry such as, for example, a debugger controls the execution unit(s) of the processor and examines the various states of the registers of the processor. By observing and controlling the state of the processor in the debug or test mode, the design and evaluation of the system incorporating the processor may be facilitated.
One technique for implementing breakpoints in a debugger is to overwrite an original instruction at the required address with a special instruction (known as a breakpoint instruction or an exception instruction), which provides control to the debugger when executed. After debugging is complete, the debugger then replaces the breakpoint instruction with the original instruction and continues execution. This technique for implementing software breakpoints may not be used with embedded processors, however, because much of the code in embedded processors might be located in read-only memories (ROMs) or semi read-only (flash) memories.
One solution to the problem of implementing breakpoints in embedded processors having ROM or flash memory is to implement hardware breakpoints using registers into which the address of a breakpoint instruction may be stored. The processor provides control to the debugger when it executes an instruction from an address that matches the address in one of the registers. Due to power and area issues, however, the number of registers and, therefore, the number of hardware breakpoints may be limited. For example, two hardware breakpoints are supported in the Intel Xscale® processor, and four hardware breakpoints are supported in the Micro-Signal Architecture (MSA) processor. The limited number of hardware breakpoints may be inadequate for debugging large applications.